The present invention relates generally to semiconductor devices and more particularly to segmented power MOSFET devices and methods for making the same.
Many modern power semiconductor devices are fabricated using lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors, sometimes referred to as lateral DMOS devices. LDMOS transistors are asymmetrical MOSFET devices, wherein a p-type channel region is diffused in a low-doped n-type drain region. Low doping on the drain side provides a large depletion layer with high blocking voltage. Moreover, the channel region diffusion can be defined with the same mask as the source region, resulting in a short channel with high current handling capabilities. Also, the relatively deep p-type diffusion causes a large radius of curvature, thereby mitigating edge effects and effectively lowering drain to source resistance when the device is turned on (Rdson). LDMOS devices often include a body contact at one end of the p-type diffusion to increase the device breakdown voltage and power handling capability.
Solenoid driver integrated circuits and other output drivers often include one or more such LDMOS power transistor devices along with logic and other lower power analog circuitry, wherein the LDMOS transistors are used to provide control outputs to solenoids in automotive or other applications. LDMOS devices have certain performance advantages in such applications, for example, such as relatively low Rdson and high blocking voltage capabilities. Thus, LDMOS devices have been widely used for integrated circuit output drivers requiring blocking voltages in the range of 20-60 volts, and a current capability in the range of about 1-3 amps or higher, although such LDMOS transistors may be employed in applications requiring other blocking voltages and current capabilities. In addition, LDMOS device fabrication is relatively easy to integrate into CMOS process flows. This allows easy integration in devices where logic, low power analog, or other circuitry is also to be fabricated in a single IC.
FIG. 1A illustrates a portion of a wafer 4 in which a solenoid driver device 2 has been fabricated, at an intermediate stage of production with a top metalization or interconnect layer having been formed. The wafer 4 includes many such devices 2, each within a die boundary 6. The device 2 includes eight LDMOS transistors 8a-8h with four transistors 8a-8d at one end and the other four transistors 8e-8h at an opposite end on either side of the die center line 10, as well as other low power analog and digital logic circuitry (not shown) in the remaining portion 12 of the usable area within the die boundary 6. The transistors 8 individually comprise a source metalization region xe2x80x9cSxe2x80x9d and a drain metalization region xe2x80x9cDxe2x80x9d, for example, wherein the transistor 8a includes a drain metalization region D1 and a source metalization region S1. Each of the transistors 8 also includes a gate (not shown). The drain metalization regions D and source metalization regions S of the transistors 8 are formed over partitioned source and drain diffusion regions (not shown) in the wafer 4, which are connected to the metalization features S and D in the illustrated top interconnect layer having lengths 16 and widths 18, which provide external connection to wiring structures 14.
The source metalization region S and the drain metalization region D of the individual LDMOS transistors 8 are separated by a distance 20, and the transistors 8 themselves are spaced from one another by a small distance 22, wherein the portion or area 12 in which other circuit devices are formed does not extend into the spacing 22 between adjacent power transistors 8. However, the close spacing 22 of the adjacent transistors 8 limits the amount of heat that can be removed from the transistors 8. As seen in FIG. 1A, lateral diffusion of heat from the partitioned source and drain regions beneath the source metalization region S1 is essentially inhibited in the direction toward the partitioned source and drain regions beneath the drain metalization region D1, and similarly, lateral thermal diffusion from the partitioned source and drain regions beneath the drain metalization region D4 is inhibited in the direction toward the source metalization region S4. Furthermore, the lateral diffusion of the inner partitioned source and drain regions beneath the source and drain metalization structures S2-S4 and D1-D3 is limited by the close adjacency thereof.
The safe operating area (SOA) of a power semiconductor device, such as the transistors 8 of the solenoid driver device 2, is a measure of the device""s ability to turn off current to a reactive load, such as a solenoid, without thermal failure or degradation. For a larger device SOA, a larger inductive current can be turned off without damaging the device. For instance, when attempting to turn off drive current to an inductive load such as a solenoid, the voltage across the device is greatly increased while the inductive load prevents the current from decreasing to zero instantaneously. For capacitive loads, the current through the device is greatly increased while the load prevents the voltage from decreasing to zero instantaneously.
In the solenoid driver device 2, the SOA is a design limitation to be considered along with the desired Rdson for the transistors 8. Due to the close spacing 22 between adjacent transistors 8, the area of the transistors 8 must be made large enough to prevent thermal damage or degradation. In the device 2 of FIG. 1A, therefore, the area occupied by the individual LDMOS devices 8 (e.g., slightly more than 2 times the length 16 times the width 18) is larger than necessary to meet a given Rdson specification, in order to prevent thermal failure during operation.
In FIG. 1B, an alternative driver device 2xe2x80x2 is illustrated, wherein the LDMOS transistors 8 have been spaced from one another by a larger distance 22xe2x80x2. However, as the transistors 8 are spaced further from one another, the area 12 in which other circuit devices are formed is reduced. In addition, it has been found that the area of unitary (e.g., unsegmented) LDMOS and other type power transistors, such as transistors 8 can only be reduced slightly by adjusting the spacing as in FIG. 1B. Thus, designers are often forced to oversize the transistors 8 beyond the area required to meet Rdson specifications, in order to achieve SOA specifications, thereby reducing the area available for other circuitry in the device 2. Thus, there is a need for power electronic devices and methods by which improved space utilization can be achieved and which facilitate smaller power transistors able to meet Rdson and SOA specifications.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
According to one aspect of the invention, transistors are provided, in which the transistor is segmented into two or more transistor segments having segment sizes or areas determined according to a safe operating area (SOA) specification for the device, which are then coupled to form a segmented transistor device. The transistor segments themselves may be further partitioned, such as comprising two or more partitioned source and drain diffusion areas or cells in the wafer. This aspect of the invention may be employed in association with LDMOS and other MOS type devices to facilitate improved space utilization and/or reduced device sizes, while achieving performance and safe operating specifications. In this regard, the various aspects of the invention may be practiced to effectively reduce the total power transistor device areas below that required for equivalent unitary (e.g., non-segmented) devices. In other implementations, the invention may be employed to provide transistors of the same or similar size or area, which have higher power handling capabilities than similarly sized non-segmented transistors.
In another aspect of the invention, the transistor segments are spaced from one another according to a pulse time specification for the device. This may be employed, for example, to provide thermal diffusion distance in the substrate between adjacent segments, through which heat is removed from the device to reduce the likelihood of thermal damage or failure during operation. In still another aspect, other electrical devices may be formed in the spaces between the power transistor segments, in order to better utilize the total area of the device die. For example, in a solenoid driver device, logic and/or low power analog circuitry such as transistors, memory cells, resistors, capacitors, diodes, or the like, may be located between the spaced power transistor segments in the substrate. Thus, in addition to facilitating reduction in the total transistor area, the invention facilitates improved space utilization (e.g., higher device density) throughout the device, by which more circuitry may be provided in a given die area, and/or by which die areas may be reduced.
Yet another aspect of the invention provides methodologies and techniques for fabricating high power MOS transistors, such as LDMOS and other devices, in which first and second transistor segments are formed in a substrate with segment areas determined according to a safe operating area specification for the transistor, and wherein the second transistor segment is spaced in the substrate from the first transistor segment based on a pulse time specification. Segmented transistors having any integer number N of such transistor segments may be thus fabricated in accordance with the methods of the invention, wherein the transistor segments may themselves be partitioned to include two or more source and drain diffusion regions or cells generally underlying the metalization structures for the transistor segments. The transistor segments individually comprise a source metalization segment, a drain metalization segment, and a gate segment, which are coupled with source, drain, and gate structures, such as pads or other conductive features. The methodologies may further comprise formation of other electrical devices in the spaces between transistor segments, for instance, to facilitate improved space utilization/device density in semiconductor devices such as solenoid and other driver integrated circuits.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.